A high performance CMOS adder

Other Title(s)

جامع عالي الأداء باستخدام تكنولوجيا ال CMOS

Dissertant

al-Akil, Wasim Fathi

Thesis advisor

Abu Gharbiyah, Khaldun

Comitee Members

Muhaydat, Khaldun
al-Qarallah, Isam A.
Mismar, Muhammad

University

Princess Sumaya University for Technology

Faculty

King Abdullah II Faculty of Engineering

Department

Department of Electrical Engineering

University Country

Jordan

Degree

Master

Degree Date

2016

English Abstract

Adders that use CMOS technology are the most common adders used in many data-processing processors to perform fast mathematical functions.

Adders are widely used in high performance very large scale integrated (VLSI) systems and chips.

Designing a low power and high speed performance VLSI circuit is one of the challenging aspects.

The CMOS Adder is one of the basic building blocks in many circuits for multiplication, division and exponentiation operations.

However, addition is a timing critical operation in almost all modern processing units.

The performance parameters such as the implementation area, the adder latency, and the power dissipation decide the choice of adders for different applications.

Moreover, there is a comprehensive research push towards designing higher speed and less complex adder circuits and architectures with lower power dissipation.

This work involves the design and simulations of a 1-bit full adder, 1-bit half adder, and 8-bit Carry Increment Adder (CIA) circuits.

The proposed adder circuits are designed and simulated using Synopsys Custom Designer Tool using 28nm technology.

The simulations results show that the proposed 16T 1-bit full adder achieves up to 66.8% improvement in average power, 53.1% improvement in SUM delay time, 64.4% improvement in Cout delay time, 72.1% improvement in SUM power delay product (PDP), and 80.1% improvement in Cout power delay product (PDP), as compared with other 1-bit conventional full adders.

The results also show that the proposed 15T 1-bit half adder circuit achieves up to 35.3% improvement in average power, 47% improvement in SUM delay time, 53.8% improvement in Cout delay time, 65.3% improvement in SUM power delay product (PDP), 70.3% improvement in Cout power delay product (PDP), and 16.6% improvement in area, compared with the other 1-bit static complementary half adders.

Further, the proposed 1-bit full adder and the proposed 1-bit half adder are used to build up an improved 8-bit CIA adder.

The results show that the improved 8-bit CIA adder gives best result in term of average power, delay time, and power delay product (PDP) compared with other 8-bit adders.

When compared with CIA adders that use conventional circuits, the improved 8-bit CIA adder achieves up to 32.5% improvement in average power, 35.4% improvement in SUM delay time, 30.8% improvement in Cout delay time, 52.9% improvement in SUM power delay product (PDP), and 48.7% improvement in Cout power delay product (PDP).

Main Subjects

Electronic engineering

No. of Pages

113

Table of Contents

• APA
• MLA
• AMA

Language

English

Data Type

Arab Theses

Record ID

BIM-720850