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Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators
Joint Authors
Peterson, Gregory D.
Harrison, Robert J.
Hinde, Robert J.
Lee, JunKyu
Source
Issue
Vol. 2010, Issue 2010 (31 Dec. 2010), pp.1-11, 11 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2010-03-01
Country of Publication
Egypt
No. of Pages
11
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
The Scalable Parallel Random Number Generators (SPRNGs) library is widely used in computational science applications such as Monte Carlo simulations since SPRNG supports fast, parallel, and scalable random number generation with good statistical properties.
In order to accelerate SPRNG, we develop a Hardware-Accelerated version of SPRNG (HASPRNG) on the Xilinx XC2VP50 Field Programmable Gate Arrays (FPGAs) in the Cray XD1 that produces identical results.
HASPRNG includes the reconfigurable logic for FPGAs along with a programming interface which performs integer random number generation.
To demonstrate HASPRNG for Reconfigurable Computing (RC) applications, we also develop a Monte Carlo π-estimator for the Cray XD1.
The RC Monte Carlo π-estimator shows a 19.1× speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1.
In this paper we describe the FPGA implementation for HASPRNG and a π-estimator example application exploiting the fine-grained parallelism and mathematical properties of the SPRNG algorithm.
American Psychological Association (APA)
Lee, JunKyu& Peterson, Gregory D.& Harrison, Robert J.& Hinde, Robert J.. 2010. Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators. VLSI Design،Vol. 2010, no. 2010, pp.1-11.
https://search.emarefa.net/detail/BIM-509101
Modern Language Association (MLA)
Lee, JunKyu…[et al.]. Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators. VLSI Design No. 2010 (2010), pp.1-11.
https://search.emarefa.net/detail/BIM-509101
American Medical Association (AMA)
Lee, JunKyu& Peterson, Gregory D.& Harrison, Robert J.& Hinde, Robert J.. Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators. VLSI Design. 2010. Vol. 2010, no. 2010, pp.1-11.
https://search.emarefa.net/detail/BIM-509101
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-509101