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Journal Articles
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders
VLSI Design. No. 2012 (2012), pp.1-13, 13 p.
Journal Articles
Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264AVC Video Encoder
By: Palomino, Daniel; Bampi, Sergio; Martina, Maurizio…[et al.]. VLSI Design. No. 2012 (2012), pp.1-20, 20 p.
Journal Articles
Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC
By: Martuza, Muhammad; Wahid, Khan A.; Martina, Maurizio. VLSI Design. No. 2012 (2012), pp.1-10, 10 p.
Journal Articles
A System View on Iterative MIMO Detection : Dynamic Sphere Detection versus Fixed Effort List Detection
By: Wu, Bin; Masera, Guido; Moy, Christophe…[et al.]. VLSI Design. No. 2012 (2012), pp.1-14, 14 p.
Journal Articles
Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics
By: Mukhopadhyay, Joyjit; Pandit, Soumya; Chen, Chien-In Henry. VLSI Design. No. 2012 (2012), pp.1-13, 13 p.
Journal Articles
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design
By: Wairya, Subodh; Nagaria, Rajendra Kumar; Monteiro, Jose Carlos…[et al.]. VLSI Design. No. 2012 (2012), pp.1-18, 18 p.
Journal Articles
Enabling Fast ASIP Design Space Exploration : An FPGA-Based Runtime Reconfigurable Prototyper
By: Pomata, Sebastiano; Tuveri, Giuseppe; Secchi, Simone…[et al.]. VLSI Design. No. 2012 (2012), pp.1-16, 16 p.
Journal Articles
Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors
By: Jan, Yahya; Jóźwiak, Lech; Lindwer, Menno M.. VLSI Design. No. 2012 (2012), pp.1-20, 20 p.
Journal Articles
9T Full Adder Design in Subthreshold Region
By: Sharma, K. G.; Singh, B. P.; Silva-Martinez, Jose…[et al.]. VLSI Design. No. 2012 (2012), pp.1-5, 5 p.
Journal Articles
Low-Complexity Hardware InterleaverDeinterleaver for IEEE 802.11agn WLAN
By: Zhang, Zhen-dong; Zhang, Xin; Yoo, Sungjoo…[et al.]. VLSI Design. No. 2012 (2012), pp.1-7, 7 p.
Journal Articles
Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks
By: Derin, Onur; Tuveri, Giuseppe; Raffo, Luigi…[et al.]. VLSI Design. No. 2012 (2012), pp.1-17, 17 p.
Journal Articles
CAD for Gigascale SoC Design and Verification Solutions
By: Hu, Shiyan; Li, Zhuo; Deng, Yangdong. VLSI Design. No. 2011 (2011), pp.1-2, 2 p.
Journal Articles
A Signature-Based Power Model for MPSoC on FPGA
By: Piscitelli, Roberta; Pimentel, Andy D.; Raffo, Luigi. VLSI Design. No. 2012 (2012), pp.1-13, 13 p.
Journal Articles
An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C
By: Walton, M.; Ahmed, O.; Peterson, Gregory D.…[et al.]. VLSI Design. No. 2012 (2012), pp.1-11, 11 p.
Journal Articles
Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm
By: Bhuvaneswari, M. C.; Sujitha, Keesarapalli; Kunz, Wolfgang…[et al.]. VLSI Design. No. 2012 (2012), pp.1-10, 10 p.
Journal Articles
Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms
By: Shanavas, I. Hameem; Gnanamurthy, Ramaswamy Kannan; Li, Zhuo. VLSI Design. No. 2011 (2011), pp.1-9, 9 p.
Journal Articles
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector : A Power-Aware Test Data Compression Method
By: Mehta, Usha S.; Dasgupta, K. S.; Deng, Yangdong…[et al.]. VLSI Design. No. 2011 (2011), pp.1-8, 8 p.
Journal Articles
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies
By: Pandit, Soumya; Patra, Amit; Tan, Sheldon…[et al.]. VLSI Design. No. 2011 (2011), pp.1-17, 17 p.
Journal Articles
A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips
By: Sun, Guanyi; Xu, Shengnan; Wang, Dawei…[et al.]. VLSI Design. No. 2011 (2011), pp.1-17, 17 p.
Journal Articles
Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity
By: Zhang, Haipeng; Qi, Ruisheng; Farquhar, Ethan…[et al.]. VLSI Design. No. 2011 (2011), pp.1-9, 9 p.
Journal Articles
Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy
By: Khan, Tareq Hasan; Wahid, Khan A.; Tourki, Rached. VLSI Design. No. 2011 (2011), pp.1-12, 12 p.
Journal Articles
Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications
By: Dhar, Subhra; Pattanaik, Manisha; Strollo, Antonio G. M.…[et al.]. VLSI Design. No. 2011 (2011), pp.1-19, 19 p.
Journal Articles
Efficient Resource Sharing Architecture for Multistandard Communication System
By: Suresh, T.; Shunmuganathan, K. L.; Deng, Yangdong. VLSI Design. No. 2011 (2011), pp.1-9, 9 p.
Journal Articles
Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies
By: Chaudhry, M. A. R.; Asad, Z.; Li, Zhuo…[et al.]. VLSI Design. No. 2011 (2011), pp.1-9, 9 p.
Journal Articles
Finding the Energy Efficient Curve : Gate Sizing for Minimum Power under Delay Constraints
By: Aizik, Yoni; Kolodny, Avinoam; Hu, Shiyan. VLSI Design. No. 2011 (2011), pp.1-13, 13 p.
Journal Articles
SoC : A Real Platform for IP Reuse, IP Infringement, and IP Protection
By: Saha, Debasri; Sur-Kolay, Susmita; Hu, Shiyan. VLSI Design. No. 2011 (2011), pp.1-10, 10 p.
Journal Articles
CONTANGO : Integrated Optimization of SoC Clock Networks
By: Lee, Dong-Jin; Markov, Igor L.; Tourki, Rached. VLSI Design. No. 2011 (2011), pp.1-12, 12 p.
Journal Articles
New Considerations for Spectral Classification of Boolean Switching Functions
By: Rice, J. E.; Muzio, J. C.; Anderson, N.…[et al.]. VLSI Design. No. 2011 (2011), pp.1-9, 9 p.
Journal Articles
The Impact of Statistical Leakage Models on Design Yield Estimation
By: Kanj, Rouwaida; Nassif, Sani; Hu, Shiyan…[et al.]. VLSI Design. No. 2011 (2011), pp.1-12, 12 p.
Journal Articles
Shedding Physical Synthesis Area Bloat
By: Li, Zhuo; Sze, Cliff; Trevillyan, Louise H.…[et al.]. VLSI Design. No. 2011 (2011), pp.1-10, 10 p.
Journal Articles
A Cost-Effective 10-Bit DA Converter for Digital-Input MOEMS Micromirror Actuation
By: Saponara, Sergio; Fanucci, Luca; Gupta, Amit Kumar…[et al.]. VLSI Design. No. 2010 (2010), pp.1-7, 7 p.
Journal Articles
Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC : A Survey
By: Mehta, Usha S.; Dasgupta, Kankar S.; Deng, Yangdong…[et al.]. VLSI Design. No. 2011 (2011), pp.1-7, 7 p.
Journal Articles
Buffer Planning for IP Placement Using Sliced-LFF
By: He, Ou; Goto, Satoshi; Hu, Shiyan…[et al.]. VLSI Design. No. 2011 (2011), pp.1-10, 10 p.
Journal Articles
Selected Papers from the Midwest Symposium on Circuits and Systems
By: Peterson, Gregory D.; Farquhar, Ethan; Blalock, Benjamin J.. VLSI Design. No. 2010 (2010), pp.1-2, 2 p.
Journal Articles
An Approach for Implementing State Machines with Online Testability
By: Lala, Parag K.; Parkerson, J. P.; Parekhji, Rubin…[et al.]. VLSI Design. No. 2010 (2010), pp.1-7, 7 p.
Journal Articles
Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits
By: Bahrebar, Poona; Navi, Keivan; Iravani, Vaez…[et al.]. VLSI Design. No. 2010 (2010), pp.1-17, 17 p.
Journal Articles
CORDIC Architectures : A Survey
By: Lakshmi, B.; Dhar, A. S.; Choi, Kiyoung. VLSI Design. No. 2010 (2010), pp.1-19, 19 p.
Journal Articles
Run-Length-Based Test Data Compression Techniques : How Far from Entropy and Power Bounds?—A Survey
By: Mehta, Usha S.; Dasgupta, Kankar S.; Devashrayee, Niranjan M.…[et al.]. VLSI Design. No. 2010 (2010), pp.1-9, 9 p.
Journal Articles
Reduced Voltage Scaling in Clock Distribution Networks
By: Mohammad, Khader; Liu, Bao; Agaian, Sos S.…[et al.]. VLSI Design. No. 2009 (2009), pp.1-7, 7 p.
Journal Articles
Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping
By: Odame, K.; Hasler, P. E.; Blalock, Benjamin J.. VLSI Design. No. 2010 (2010), pp.1-8, 8 p.
Journal Articles
Low-Cost Allocator Implementations for Networks-on-Chip Routers
By: Zhang, Min; Choy, Chiu-Sing; Palesi, Maurizio. VLSI Design. No. 2009 (2009), pp.1-10, 10 p.
Journal Articles
FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme
By: Sumathi, P.; Janakiraman, P. A.; Farquhar, Ethan. VLSI Design. No. 2010 (2010), pp.1-11, 11 p.
Journal Articles
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs
By: Zhu, Yan; Sin, Sai-Weng; Seng-Pan U…[et al.]. VLSI Design. No. 2010 (2010), pp.1-8, 8 p.
Journal Articles
Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs
By: Hashemian, Reza; Blalock, Benjamin J.. VLSI Design. No. 2010 (2010), pp.1-12, 12 p.
Journal Articles
Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations
By: Yelamarthi, Kumar; Chen, Chien-In Henry; Farquhar, Ethan. VLSI Design. No. 2010 (2010), pp.1-13, 13 p.
Journal Articles
Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators
By: Lee, JunKyu; Peterson, Gregory D.; Farquhar, Ethan…[et al.]. VLSI Design. No. 2010 (2010), pp.1-11, 11 p.
Journal Articles
A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs
By: Gothandaraman, Akila; Warren, G. Lee; Farquhar, Ethan…[et al.]. VLSI Design. No. 2010 (2010), pp.1-8, 8 p.
Journal Articles
Error Immune Logic for Low-Power Probabilistic Computing
By: Marr, Bo; George, Jason; Hasler, P. E.…[et al.]. VLSI Design. No. 2010 (2010), pp.1-9, 9 p.
Journal Articles
Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments
By: Merchant, Saumil G.; Peterson, Gregory D.; Farquhar, Ethan. VLSI Design. No. 2010 (2010), pp.1-25, 25 p.
Journal Articles
Post-CTS Delay Insertion
By: Lu, Jianchao; Taskin, Baris; Peterson, Gregory D.. VLSI Design. No. 2010 (2010), pp.1-9, 9 p.
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